1. Field of the Invention
The present invention relates to a variable delay circuit such as a digital DLL (Delayed Locked Loop) circuit, and a semiconductor integrated circuit device equipped with such as a DLL circuit.
Recently, there has been considerable advance of the operation speed and integration density of semiconductor integrated circuit devices. Under the above situation, it is required to provide a clock signal synchronized with an external clock signal to a given circuit. More particularly, a synchronous DRAM device (hereinafter simply referred to as an SDRAM device) is required to supply a clock signal synchronized with an external clock signal to output buffer circuits. Such a clock signal can be obtained through a DLL circuit, which receives the external clock signal. As the frequency of the DLL circuit is increased, the DLL circuit is required to be configured with higher precision. In order to meet the above requirement, the DLL circuit should be equipped with a variable delay circuit having high precision.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional variable delay circuit. The circuit shown in FIG. 1 includes a plurality of delay elements, for example, 10 delay elements G1 through G10, which are connected in series. Hereinafter, the delay elements G1 through G10 are referred to as gates. Each of the gates G1 through G10 has a unit delay time td. The inputs of the gates G1 through G10 are operably connected to an input node IN through switches SW1 through SW10, respectively. The output of the gate G10 is connected to an output node OUT.
The ON/OFF of the switches SW1 through SW10 are controlled by a control circuit, which is not shown in FIG. 1. The control circuit closes one of the switches SW1 through SW10 in accordance to a necessary delay time. In FIG. 1, only the switch SW7 is closed. A signal applied to the input node IN passes through four gates G7 through G10 and is thus delayed by 4 td. That is, the output signal obtained at the output node OUT lags behind the input signal applied to the input node IN by 4 td. The variable delay circuit is capable of defining the delay time between td and 10 td by selecting one of the switches SW1 through SW10.
It should be noted that the variable delay circuit shown in FIG. 1 can provide the delay times equal to an integer multiple of the unit delay time td. In other words, the variable delay circuit shown in FIG. 1 cannot define the delay time at a precision (step) less than the unit delay time td. For example, the circuit cannot define a delay time of 2.5 td.
If a semiconductor integrated circuit device such as an SDRAM device operates at a relatively low operation frequency, the conventional delay circuit shown in FIG. 1 can be equipped with the device. The digital DLL circuit built in the SDRAM device produces an internal clock signal synchronized the external clock signal. Hence, an influence of a clock signal line formed on the SDRAM device can be eliminated from the internal clock signal, and data can be output to the outside of the device in synchronism with the external clock signal. However, if the SDRAM device is required to operate at a frequency as high as 100 MHz, the DLL circuit which should be mounted on the SDRAM device is required to have a capability of finer delay control.
As has been described previously, the digital DLL circuit has a delay circuit made up of a plurality of gates (unit delay circuits) connected in series, the gates being formed of logic gates. Usually, the unit delay circuit has a minimum delay time approximately equal to 200 ps. In order to realize the SDRAM device which operates at an operation frequency equal to or higher than 100 MHz, the digital DLL circuit is required to realize a fine delay control in which a delay time less than 200 ps can be controlled. In principle, the precision of the delay control can be improved by using a unit delay circuit having a delay time less than 200 ps.
However, the DLL circuit employing such a fine unit delay circuit requires a large number of unit delay elements in order to ensure a certain delay time. In this case, an increased circuit scale should be realized on the chip.
It is an object of the present invention to provide a novel and useful variable delay circuit capable of controlling the delay time with a high precision.
Another object of the present invention is to provide a compact variable delay circuit which can be configured without an increase in the circuit scale.
A further object of the present invention is to provide a semiconductor integrated circuit device equipped with a variable delay circuit as described above.
The above objects of the present invention are achieved by a variable delay circuit comprising: a first gate having a first delay amount; and a second gate having a second delay amount greater than the first delay amount, a difference between the first delay amount and the second delay time being less than the first delay amount.
The above objects of the present invention are also achieved by a variable delay circuit comprising: a first gate line which has first gates cascaded via intermediate nodes and receives an input signal; a second gate line which has second gates cascaded via intermediate nodes, the second gates having a delay amount different from that of the first gates; and switches respectively connecting the intermediate nodes of the first gate line and those of the second gate line. One of the switches is closed to connect the first gate line and the second gate line together so that the input signal applied to the first gate line passes through a part of the first gate line, the one of the switches, and a part of the second gate line.
The above variable delay circuit may be configured so that: the first gate line includes n first gates; and each of the second gates has the following delay amount:
[(n+1)/n]td
where td denotes the delay time of each of the first gates.
The above objects of the present invention are also achieved by a variable delay circuit comprising: a first gate line which has first gates cascaded via intermediate nodes and receives an input signal; a second gate line which has second gates cascaded via intermediate nodes; and switches respectively connecting the intermediate nodes of the first gate line and those of the second gate line. One of the switches is closed to connect the first gate line and the second gate line together so that the input signal applied to the first gate line passes through a part of the first gate line, the one of the switches, and a part of the second gate line, the intermediate nodes of the first gate line having a wiring load different from that of the intermediate nodes of the second gate line.
The above objects of the present invention are also achieved by a variable delay circuit comprising: a first gate line which has first gates cascaded via intermediate nodes and receives an input signal; a second gate line which has second gates cascaded via intermediate nodes, the second gates having a delay amount different from that of the first gates; switches respectively connecting the intermediate nodes of the first gate line and those of the second gate line; and a control circuit which turns ON one of the switches being closed to connect the first gate line and the second gate line together so that an output signal obtained by causing the input signal applied to the first gate line to pass through a part of the first gate line, the one of the switches, and a part of the second gate line and the input signal have a given phase difference.
The above objects of the present invention are also achieved by a variable delay circuit comprising: a first gate line which has first gates cascaded via intermediate nodes and receives an input signal; a second gate line which has second gates cascaded via intermediate nodes, the intermediate nodes of the first gate line having a wiring load different from that of the intermediate nodes of the second gate line; switches respectively connecting the intermediate nodes of the first gate line and those of the second gate line; and a control circuit which turns ON one of the switches being closed to connect the first gate line and the second gate line together so that an output signal obtained by causing the input signal applied to the first gate line to pass through a part of the first gate line, the one of the switches, and a part of the second gate line and the input signal have a given phase difference.
The above variable delay circuit may be configured so that the control circuit comprises: a third gate line which has third gates cascaded and receives the input signal; a fourth gate line which has fourth gates cascaded and receives the output signal; phase comparators which are provided between the intermediate nodes of the third gate line and those of the fourth gate line and compare the phases of the input signal and the output signal with each other at the intermediate nodes; and logic gates each receiving output signals of two adjacent phase comparators among the phase comparators. The switches are controlled by respective output signals of the logic gates.
The above variable delay circuit may be configured so that each of the phase comparators comprises: a first flip-flop connected to one of the intermediate nodes of the third gate line and one of the intermediate nodes of the fourth gate line; a second flip-flop which outputs the output signal of the phase comparator to the corresponding one of the logic gates; and a gate circuit which is provided between the first and second flip-flops and supplies output signals of the first flip-flop to the second flip-flop with a delay.
The above variable delay circuit may be configured so that the control circuit comprises: a third gate line which has third gates cascaded and receives the input signal; a fourth gate line which has fourth gates cascaded and receives the output signal; phase comparators which are provided between the intermediate nodes of the third gate line and those of the fourth gate line and compare the phases of the input signal and the output signal with each other at the intermediate nodes; and logic gates each receiving output signals of two adjacent phase comparators among the phase comparators. The switches are controlled by respective output signals of the logic gates.
The above variable delay circuit may be configured so that each of the phase comparators comprises: a first flip-flop connected to one of the intermediate nodes of the third gate line and one of the intermediate nodes of the fourth gate line; a second flip-flop which outputs the output signal of the phase comparator to the corresponding one of the logic gates; and a gate circuit which is provided between the first and second flip-flops and supplies output signals of the first flip-flop to the second flip-flop with a delay.
The above objects of the present invention are also achieved by a semiconductor integrated circuit device comprising: a first DLL (Delayed Locked Loop) circuit which delays an input signal; and a second DLL circuit which has a precision higher than that of the first DLL circuit, the first DLL circuit performing a phase control operation independently of that of the second DLL circuit, a delay amount control of the second DLL circuit depending on that of the first DLL circuit, and the input signal being delayed by the first and second DLL circuits so that an output signal thus obtained has a given phase relationship with the input signal.
The above semiconductor integrated circuit device may be configured so that: the second DLL circuit is in a reset state when the first DLL circuit performs the delay amount control; and the second DLL circuit performs the delay amount control when the input signal and the output signal are pulled in phase by the first DLL circuit.
The above semiconductor integrated circuit device may be configured so that: when the first DLL circuit has a precision td, the second DLL circuit can control a delay amount including a range of xc2x1td; and when the input signal and the output signal have a phase difference exceeding the range xc2x1td in the first DLL, the first DLL circuit outputs a reset signal to the second DLL circuit so that the second DLL circuit is caused to have a predetermined delay amount.
The above semiconductor integrated circuit device may be configured so that the predetermined delay amount of the second DLL circuit is equal to half of a variable delay amount range of the second DLL circuit.
The above semiconductor integrated circuit device may be configured so that: each of the first and second DLL circuits has first and second routes through which the input signal passes; and the second routes of the first and second DLL circuits are dummy delay circuits which provide the same delay amounts as those of the first routes of the first and second DLL circuits.
The above semiconductor integrated circuit device may be configured so that: the second DLL circuit includes first and second delay elements having mutually different delay amounts; and a difference between the delay amounts of the first and second delay elements corresponds to a precision of the second DLL circuit.
The above semiconductor integrated circuit device may be configured so that: the first DLL circuit includes first and second flip-flops; the first flip-flop has a set terminal which receives a delayed version of a first clock signal related to the input signal obtained through a first delay element and a reset terminal which receives a second clock signal related to the output signal; the second flip-flop has a set terminal which receives a delayed version of the second clock signal obtained through a second delay element and a reset terminal which receives the first clock signal; and output signals of the first and second flip-flops indicating a result of a phase comparing operation for the phase control operation.
The above semiconductor integrated circuit device may be configured so that: each of the first and second flip-flops has first and second NAND gates; the first NAND gate has a first input terminal which serves as the set terminal, a second input terminal, and an output terminal; and the second NAND gate has a first input terminal which serves as the reset terminal, a second input terminal which is connected to the output terminal of the first NAND gate and forms an output terminal Q, and an output terminal which is connected to the second input terminal of the first NAND gate and forms an output terminal /Q.
The above semiconductor integrated circuit device may be configured so that: each of the first and second flip-flops has first and second NAND gates; the first NAND gate has a first input terminal, a second input terminal which serves as the set terminal, and an output terminal; and the second NAND gate has a first input terminal which is connected to the output terminal of the first NAND gate and forms an output terminal /Q, a second input terminal which serves as the reset terminal, and an output terminal which is connected to the first input terminal of the first NAND gate and forms an output terminal Q.
The above semiconductor integrated circuit device may be configured so that: each of the first and second NAND gates has first and second P-channel transistors and first and second N-channel transistors; the first P-channel transistor has a source connected to a first power source, a gate connected to a first input terminal, and a drain connected to an output terminal; the second P-channel transistor has a source connected to the first power source, a gate connected to a second input terminal, and a drain connected to the output terminal; the first N-channel transistor has a source connected to a drain of the second N-channel transistor, a gate connected to the first input terminal, and a drain connected to the output terminal; and the second N-channel transistor has a source connected to the second power source, a gate connected to the second input terminal, and the drain.
The above semiconductor integrated circuit device may be configured so that: each of the first and second NAND gates has first and second P-channel transistors and first and second N-channel transistors; the first P-channel transistor has a source connected to a first power source, a gate connected to a first input terminal, and a drain connected to an output terminal; the second P-channel transistor has a source connected to the first power source, a gate connected to a second input terminal, and a drain connected to the output terminal; the first N-channel transistor has a source connected to a drain of the second N-channel transistor, a gate connected to the first input terminal, and a drain connected to the output terminal; and the second N-channel transistor has a source connected to the second power source, a gate connected to the second input terminal, and the drain.
The above semiconductor integrated circuit device may be configured so that the first and second delay elements have a circuit configuration identical to that of one stage of the first DLL circuit.
The above semiconductor integrated circuit device may be configured so that the first and second DLL circuits have respective delay circuits which are formed by a combination of logic elements.
The above semiconductor integrated circuit device may be configured so that: the first and second delay elements are formed by logic elements; and the first delay element has a fan-out different from that of the second delay element.
The above semiconductor integrated circuit device may be configured so that: the first and second delay elements are formed by logic elements; and the first delay element is supplied with a power supply voltage different from that supplied to the second delay element.
The above semiconductor integrated circuit device may be configured so that the second DLL circuit comprises a delay circuit which includes at least one of a capacitance and a resistance.
The above semiconductor integrated circuit device may be configured so that the second DLL circuit comprises a delay circuit which includes a variable capacitance which is controlled so that the given phase relationship can be obtained.
The above semiconductor integrated circuit device may be configured so that the second DLL circuit comprises a delay circuit which includes a variable resistance which is controlled so that the given phase relationship can be obtained.
The above semiconductor integrated circuit device may be configured so that the second DLL circuit comprises a delay circuit which includes a capacitance and resistance which are controlled so that the given phase relationship can be obtained.
The above semiconductor integrated circuit device may be configured so that: the second DLL circuit includes a delay circuit having a shift register; and the predetermined delay amount of the second DLL circuit corresponds to a center position of the shift register.
The above semiconductor integrated circuit device may be configured so that the first and second delay elements include at least one of a capacitance and a resistance.
The above semiconductor integrated circuit device may be configured so that the first and second delay elements comprise a variable capacitance which is controlled so that the given phase relationship can be obtained.
The above semiconductor integrated circuit device may be configured so that the first and second delay elements comprise a delay circuit which includes a variable resistance which is controlled so that the given phase relationship can be obtained.
The above semiconductor integrated circuit device may be configured so that the first and second delay elements comprise a delay circuit which includes a capacitance and resistance which are controlled so that the given phase relationship can be obtained.
The above semiconductor integrated circuit device may be configured so that: the first and second DLL circuits comprise respective delay circuits; and the delay circuit of the second DLL circuit has a variable range exceeding that defined by the precision of the delay circuit of the first DLL circuit.
The aforementioned objects of the present invention are achieved by a semiconductor integrated circuit device comprising: a first DLL (Delayed Locked Loop) circuit which delays an input signal; and a second DLL circuit which has a precision higher than that of the first DLL circuit, the second DLL circuit operating independently of the first DLL circuit, the input signal being delayed by the first and second DLL circuits so that an output signal thus obtained has a given phase relationship with the input signal.
The above semiconductor integrated circuit device may be configured so that: the first DLL circuit comprises a first controller which performs a delay control so that the input and output signals have the given phase relationship with the precision of the first DLL circuit; and the second DLL circuit comprises a second controller which performs a delay control so that the input and output signals have the given phase relationship with the precision of the second DLL circuit.
The above semiconductor integrated circuit device may be configured so that the second DLL circuit comprises: a comparator which determines whether the phase difference between the input signal and the output signal corresponds to one of n predetermined phase differences where n is an integer; and a delay circuit which has a delay amount corresponding to the one of the n predetermined phase differences.
The above semiconductor integrated circuit device may be configured so that the delay circuit comprises a circuit which provides delay amounts which respectively correspond to the n predetermined phase differences.
The above semiconductor integrated circuit device may be configured so that: the comparator comprises n delay circuits which have respective delay amounts corresponding to the n phase differences; and the input signal is compared with output signals of the n delay circuits.
The above semiconductor integrated circuit device may be configured so that the second DLL circuit is provided at an output side of the first DLL circuit.
The above semiconductor integrated circuit device may be configured so that the delay circuit comprises delay parts having different delay amounts, each of the delay parts having at least one of a capacitance and a resistance.
The above semiconductor integrated circuit device may be configured so that the delay circuit comprises delay parts having different delay amounts, the delay parts including respective logic elements having mutually different delay amounts.
The above semiconductor integrated circuit device may further comprise a memory array, wherein data read from the memory array can be output to an external circuit in synchronism with the output signal.
The above semiconductor integrated circuit device may further comprise a memory array, wherein data read from the memory array can be output to an external circuit in synchronism with the output signal.
It is another object of the present invention to provide a phase comparator circuit comprising: a first flip-flop which is supplied with first and second signals and makes a decision whether the first signal leads to the second signal; a first delay circuit which delays the first signal by a first delay amount; a second delay circuit which delays the second signal by a second delay amount different from the first delay amount; and a second flip-flop which is supplied with an output signal of the first delay circuit and an output signal of the second delay circuit and makes a decision whether the output signal of the first delay circuit leads to the output signal of the second delay circuit.